1. Field of the Invention
The present invention relates generally to a refresh control circuit and method thereof and a bank address signal change circuit and methods thereof, and more particularly to a refresh control circuit with reduced power consumption and method thereof and a bank address signal change circuit with reduced power consumption and methods thereof.
2. Description of the Related Art
In a conventional semiconductor memory device, such as a dynamic random access memory (DRAM), a current leakage may affect data stored in a memory cell. Memory cells of the semiconductor memory device may be periodically refreshed with a refreshing operation to recharge or refresh the data stored in the memory cells. The refreshing operation may be performed by controlling an internal address of the semiconductor memory device, where the internal address may be adjusted during the refreshing operation by a command signal (e.g., an externally received command signal).
Conventional semiconductor memory devices may include a plurality of memory banks on each of a plurality of memory chips. Each of the plurality of memory banks may store a given amount of data (e.g., in a plurality of memory cells). In an example, a power consumption of a semiconductor memory device may be reduced so as to conform to power requirements in application-specific devices (e.g., a Pentium-level computer, a wireless telephone, a data bank, a personal data assistance (PDA) system, etc.).
The refreshing operation may be performed at each of the plurality of memory banks irrespective of whether data is actually stored in memory cells of a refreshed memory bank, which may reduce an efficiency of the refreshing operation due to wasteful refreshes of memory cells not including data.
A Partial Array Self Refresh (PASR) operation may reduce an inefficiency of the refreshing operation due to wasteful refreshes. The PASR operation may include performing the refreshing operation only on memory banks with memory cells storing data, which may reduce a number of wasteful refreshes.
Each of FIGS. 1, 2 and 3 illustrates a conventional semiconductor memory device having memory banks 10a, 10b, 10c and 10d, where the PASR operation is applied to at least one of the memory banks 10a/10b/10c/10c 
In each of FIGS. 1, 2 and 3, during the PASR operation, a refreshing operation area may be selected by a Mode Register Set (MRS) code signal. The MRS code signal may indicate a full array mode, a half array mode, a quarter array mode or other mode, as will be described below with respect to FIGS. 1, 2 and 3, respectively.
FIG. 1 illustrates the PASR operation operating in accordance with the full array mode in a conventional semiconductor memory device. Referring to FIG. 1, the PASR operation may be set to the full array mode to perform a refreshing operation at each of the memory banks 10a, 10b, 10c and 10d based on bank address signals BA0 and BA1.
FIG. 2 illustrates the PASR operation operating in accordance with the half array mode in a conventional semiconductor device. Referring to FIG. 1, the PASR operation may be set to the half array mode to perform a refreshing operation at the memory banks 10a and 10b based on the bank address signals BA0 and BA1.
FIG. 3 illustrates the PASR operation operating in accordance with the quarter array mode in a conventional semiconductor device. Referring to FIG. 1, the PASR operation may be set to the quarter array mode to perform a refreshing operation at the memory bank 10a based on the bank address signals BA0 and BA1.
Referring to FIGS. 1, 2 and 3, if the first bank address signal BA0 is set to a first logic level (e.g., a higher logic level or logic “1”) and the second bank address signal BA1 is set to a second logic level (e.g., a lower logic level or logic “0”), the memory bank 10b may be selected for refreshing by the PASR operation. If the first and second bank address signals BA0 and BA1 are set to the second logic level (e.g., a lower logic level or logic “0”), the memory bank 10a may be selected for refreshing by the PASR operation. If the first address signal BA0 is set to the second logic level and the second address signal BA1 is set to the first logic level, the memory bank 10c may be selected for refreshing by the PASR operation. If the first and second bank address signals BA0 are set to the first logic level, the memory bank 10d may be selected for refreshing by the PASR operation.
As shown in FIGS. 1, 2 and 3, the refreshing operation may be reduced by the PASR operation to apply to less than all of the memory banks by the quarter array mode and the half array mode settings. However, in conventional semiconductor memory devices supporting the PASR operation, the memory bank or banks selected for the refreshing operation in the half array mode and the quarter array mode array mode may be predetermined.
For example, in the half array mode operation, the memory bank 10a and the memory bank 10b may each be refreshed, as illustrated in FIG. 2, and the memory bank 10a may be refreshed in the quarter array mode. Power consumption may increase in conventional semiconductor memory devices employing the PASR operation because different memory banks may have different refresh cycles and selected memory banks for the refreshing operation may have shorter refresh cycles as compared to non-selected memory banks.